ASAP11

ASAP 2011 — 22nd IEEE International Conference on
Application-specific Systems, Architectures and Processors


September 11-14, 2011,   Santa Monica, California, USA

 

Santa Monica PierSanta Monica ParkGetty Center



Program Chairs

Joseph Cavallaro, Rice University, USA

Paolo Ienne, EPFL, Switzerland

Alex Tenca, Synopsys, USA

Program

 Best Paper Award

An FPGA architecture for solving the Table Maker's Dilemma

Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, and Alexandru Plesco


Monday, September 12

 
Hosted by: Milos D. Ercegovac

9:00    Welcome and introduction
 

9:30-10:30  Keynote talk: Era of Customization and Specialization

Jason Cong, UCLA

10:30-11:00 Coffee break
 
11:00-12:30 Session 1 - Reconfigurable Systems

Session chair: Jason Cong

 
CusComNet: A Customisable Network for Reconfigurable Heterogeneous Clusters

Stewart Denholm, Kuen Hung Tsoi, Peter Pietzuch, and Wayne Luk

 
Address Generation Scheme for a Coarse Grain Reconfigurable Architecture

Muhammad Ali Shami and Ahmed Hemani

 
Accelerating Vision and Navigation Applications on a Customizable Platform

Jason Cong, Beayna Grigorian, Glenn Reinman, and Marco Vitanza

 
12:30-14:00 Lunch Break
 
14:00-15:30 Session 2- Computer Arithmetic and Algorithms

Session chair: Jean-Michel Muller

 
A High-Performance, Low-Power Linear Algebra Core

Ardavan Pedram, Andreas Gerstlauer, and Robert A. van de Geijn

 
A Decimal Floating-Point Fused Multiply-Add Unit with a Novel Decimal Leading-Zero Anticipator

Ahmet Akkas and Michael J. Schulte

 
Longest Prefix Match and Updates in Range Tries

Ioannis Sourdis and Sri Harsha Katamaneni

 
15:30-16:30 Poster Session 1 - CAD, Reconfigurable Systems, Multi-Core Processors
 
Efficient Custom Instruction Enumeration for Extensible Processors

Chenglong Xiao and Emmanuel Casseau

 
IP-XACT Extensions for Reconfigurable Computing

Razvan Nane, Sven van Haastregt, Todor Stefanov, Bart Kienhuis, Vlad Mihai Sima, and Koen Bertels


An Integrated Development Toolset and Implementation Methodology for Partially Reconfigurable System-on-Chips

Abelardo Jara-Berrocal and Ann Gordon-Ross

 
Cooperative Multitasking for Heterogeneous Hardware Accelerators in the Linux Completely Fair Scheduler

Tobias Beisel, Tobias Wiersema, Christian Plessl, and André Brinkmann

 
Optimal Design-Space Exploration of Streaming Applications

Shobana Padmanabhan, Yixin Chen, and Roger D. Chamberlain

 
Stack Data Management for Limited Local Memory (LLM) Multi-core Processors

Ke Bai, Aviral Shrivastava, and Saleel Kudchadker

 
16:30-17:30 Session 3 - System Profiling

Session chair: Koen Bertels

 
Low-Cost Hardware Profiling of Run-Time and Energy in FPGA Embedded Processors

Mark Aldham, Jason Anderson, Stephen Brown, and Andrew Canis


TimeTrial: A Low-Impact Performance Profiler for Streaming Data Applications

Joseph M. Lancaster, E. F. Berkley Shands, Jeremy D. Buhler, and Roger D. Chamberlain
 
 
Hosted by: Earl Swartzlander

19:00-20:30 Dinner and Talk

More than 50 years of Parallel Processing and Still No Easy Path to Speedup

Michael Flynn, Stanford

 
 
Tuesday, September 13

 
9:00-10:30 Session 4 - Multi-Core Processors and Networks

Session chair: Gang Qu

 
System-Level Design Space Exploration for Dedicated Heterogeneous Multi-Processor Systems

Luigi Pomante

 
Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays

Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, and Juergen Teich


Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAs

Oguzhan Erdem, Hoang Le, Viktor K. Prasanna, and Cuneyt F. Bazlamacı

 
10:30-11:30 Poster Session 2 - Applications, Arithmetic, Image Processing, Wireless
 
An Energy Efficient Adaptive Event Detection Scheme for Wireless Sensor Network

Zheng Zhou and Gang Qu


Architecture Model for Approximate Tandem Repeat Detection

Tomáš Martinek and Matej Lexa

 
Design of a High Performance FPGA Based Fault Injector for Real-Time Safety-Critical Systems

Marko Miklo, Carl R. Elks, and Ronald D. Williams


Domain-Specific Processor with 3D Integration for Medical Image Processing

Jason Cong, Karthik Guruaj, Muhuan Huang, Sen Li, Bingjun Xiao, and Bingjun Zou


A Parallel k-Partition Method to perform Montgomery Multiplication

 Joao Carlos Neto, Alexandre Ferreira Tenca, and Wilson Vicente Ruggiero

 
A Residue Logarithmic Number System ALU Using Interpolation and Cotransformation

Mark G. Arnold, Ioannis Kouretas, and Vassilis Paliouras


Design and Implementation of a Belief Propagation Detector for Sparse Channels

Yanjie Peng, Kai Zhang, Andrew G. Klein, and Xinming Huang

 
Hosted by: Earl Swartzlander

11:30-12:30 Keynote talk: Architectures for Green Routers

Viktor Prasanna, USC

 
12:30-14:00 Lunch Break
 
14:00-15:30 Session 5 - Communication Systems

Session chair: Roger Chamberlain

 
An Area-Efficient LDPC Decoder For Multi-Standard With Conflict Resolution

Changsheng Zhou, Yunlong Ge, Xubin Chen, Yun Chen, and Xiaoyang Zeng


High Throughput Contention-free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder

Guohui Wang, Yang Sun, Joseph R. Cavallaro, and Yuanbin Guo

 
Energy-efficient floating-point arithmetic for software defined radio architectures

Syed Zohaib Gilani, Nam Sung Kim, and Michael J. Schulte

 
15:30-16:00 Coffee break
 
16:00-17:30 Session 6 - GPU and Accelerators

Session chair: Mike Schulte

 
On the Performance of GPU Public-Key Cryptography

Samuel Neves and Filipe Araujo

 
Exploiting Structural Redundancy of SIMD Accelerators for their Built-In Self-Testing/Diagnosis and Reconfiguration

Alessandro Strano, Davide Bertozzi, Arnaud Grasset, and Sami Yehia

 
Accelerating the Photon Mapping Algorithm and its Hardware Implementation

Shawn Singh, Seung Hyun Pan, and Miloš D. Ercegovac

 
Wednesday, September 14

 
9:00-10:30 Session 7 - Image Processing

Session chair: Frank Hannig

 
A Low Power Fault-Tolerance Architecture for the Kernel Density Estimation Based Image Segmentation Algorithm

Peng Li and David J. Lilja

 
Instruction Set Extension for High Throughput Disparity Estimation in Stereo Image Processing

Christian Banz, Carsten Dolar, Fabian Cholewa, and Holger Blume
 
Low Energy Motion Estimation via Selective Approximations

Yunus Emre and Chaitali Chakrabarti

 
10:30-11:00 Coffee break
 
11:00-12:30 Session 8 - FPGA Applications

Session chair: Wayne Luk

 
An FPGA architecture for solving the Table Maker's Dilemma (Best Paper Award)

Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, and Alexandru Plesco

 
Next-Generation Massively Parallel Short-Read Mapping on FPGAs

Oliver Knodel, Thomas B. Preuser, and Rainer G. Spallek

 
An FPGA-based Real-Time Non-uniformity Correction System for Infrared Focal Plane Arrays

Rodolfo Redlich, Gonzalo Carvajal, and Miguel Figueroa

 





ASAP 2011 is organized by

IEEE

and sponsored by IEEE Technical Committee on VLSI






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