Contents

1. INTRODUCTION   2. SPECIFICATION OF COMBINATIONAL SYSTEMS   3. COMBINATIONAL ICs: CHARACTERISTICS AND CAPABILITIES   4. DESCRIPTION AND ANALYSIS OF GATE NETWORKS   5. DESIGN OF COMBINATIONAL SYSTEMS: TWO-LEVEL GATE NETWORKS   6. DESIGN OF COMBINATIONAL SYSTEMS: MULTI-LEVEL GATE NETWORKS   7. SPECIFICATION OF SEQUENTIAL SYSTEMS   8. SEQUENTIAL NETWORKS   9. STANDARD COMBINATIONAL MODULES 10. ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 11. STANDARD SEQUENTIAL MODULES 12. PROGRAMMABLE MODULES 13. REGISTER-TRANSFER LEVEL (RTL) SYSTEMS 14. DATA AND CONTROL SUBSYSTEMS 15. SPECIFICATION AND IMPLEMENTATION OF A MICROCOMPUTER Appendix A BOOLEAN ALGEBRAS CD-ROM: Altera MAX-II PLUS  1. INTRODUCTION 1.1 About digital systems 1          • What is a digital system?           • Why are digital systems important?           • When are digital systems used          • Combinational and sequential systems  1.2 Specification and implementation, analysis and design 6          • Structured analysis and design           • Levels of  implementation 1.3 Computer-aided design tools 10 1.4 Further readings 11 2. SPECIFICATION OF COMBINATIONAL SYSTEMS  2.1 Combinational systems: definition and specification levels 12 2.2 High-level specification of combinational systems 14 2.3 Data representation and coding 16          • Representation of characters           • Representation of positive integers  2.4 Binary specification of combinational systems 21          • Switching functions           • Switching expressions  2.5 Examples of specifications 37 2.6 Specification using VHDL 39 2.7 Further readings 52 Exercises 52  TOP 3. COMBINATIONAL ICs: CHARACTERISTICS AND CAPABILITIES 3.1 Representation of binary variables 60 3.2 Structure and operation of CMOS gates 62 n-type and p-type switches 62 NOT gate 63 NAND and NOR gates 64 AND and OR gates 65 Complex gates 65 Transmission gate, XOR gate, and 2-input multiplexer 67 3.3 Propagation delays, transition times and effect of load 68 3.4 Voltage variations and noise margins 71 3.5 Power dissipation and delay-power product 71 3.6 Buses and three-state drivers 72 3.7 Circuit characteristics of a CMOS family 74 3.8 Evolution in the implementation of digital systems 74 3.9 VLSI circuit-level design styles 77 3.10 Packaging level: chips, boards, and cabinets 78 3.11 VHDL description of gates 78 3.12 Further readings 83 Exercises 84 TOP 4. DESCRIPTION AND ANALYSIS OF GATE NETWORKS 88 4.1 Definition of gate networks 89 4.2 Description and characteristics of gate networks 90 4.3 Sets of gates 120 Universal set 92 4.4 Analysis of gate networks 94 4.5 Description of gate networks using VHDL 103 4.6 Further readings 83      Exercises 84 TOP 5. DESIGN OF COMBINATIONAL SYSTEMS: TWO-LEVEL GATE NETWORKS 112 5.1 Minimal two-level networks 112 5.2 Karnaugh maps 115 5.3 Minimization of sum of products and product of sums 121       • Sum of products        • Products of sums        • Examples of design of minimal two-level gate network        • Tabular methods  5.4 Design of multiple-output two-level gate networks 131 5.5 Two-level NAND-NAND and NOR-NOR networks 134 5.6 Limitations of two-level networks 135 5.7 Programmable modules: PLAs and PALs 136 5.8 Further readings 141      Exercises 142  TOP 6. DESIGN OF COMBINATIONAL SYSTEMS: MULTI-LEVEL GATE NETWORKS 144 6.1 Typical transformations to meet network requirements 145 6.2 Alternative implementations 152 6.3 Networks with XOR and XNOR gates 154 6.4 Networks with 2-input multiplexers 155 6.6 Further readings 158      Exercises 159  TOP 7. SPECIFICATION OF SEQUENTIAL SYSTEMS 161 7.1 Synchronous sequential systems 161      • State description of finite-state systems       • Mealy and Moore machines 7.2 Representation of the state-transition and output functions 167       • State diagram       • State names  7.3 Time behavior and finite-state machines 170       • Input-output sequence pairs from state description       • State description from time behavior  7.4 Finite-memory sequential systems 173 7.5 Controllers 173  7.6 Equivalent sequential systems 174       • State description with redundant states        • Equivalent states       • Procedure to minimize the number of states 7.7 Binary specification of sequential systems 182 7.8 Specification of different types of sequential systems 183       • Modulo-p counter        • Pattern recognizer  7.9 Specification of sequential systems in VHDL 186 7.10 Further readings 188        Exercises 189 TOP 8. SEQUENTIAL NETWORKS 195 8.1 Canonical form of sequential networks 195 8.2 High-level and binary implementations 197 8.3 Gated-latch and D flip-flop 198 8.4 Timing characteristics of sequential networks 205 8.5 Analysis of canonical sequential networks 209 8.6 Design of canonical sequential networks 212 8.7 Other flip-flop modules: SR, JK,  T  214 8.8 Analysis of networks with flip-flops 216 8.9 Design of networks with flip-flops 221 8.10 Design using special state assignments 226         •  One-flip-flop-per-state         •  Shifting state register 8.11 Description of flip-flops and sequential networks in VHDL 229 8.12 Further readings 234        Exercises 235  TOP 9. STANDARD COMBINATIONAL MODULES 241 9.1 Binary decoders 241  •  Binary decoder and OR gate as universal set •  Decoder networks  9.2 Binary encoders 250 9.3 Priority encoders 254 9.4 Multiplexers (selectors) 257       •  Multiplexer as universal combinational module       •  Multiplexer trees  9.5 Demultiplexers (distributors) 262 9.6 Shifters 264 9.7 Implementation of modules 269 9.8 Further readings 270      Exercises 270 TOP 10. ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 270 10.1 Adder modules for positive integers 278 10.2 Networks of adder modules 286 10.3 Representation of signed integers and basic operations 288         •  Representation and sign detection         •  Addition and subtraction of signed integers 10.4 ALU modules and networks 298 10.5 Comparator modules 300 10.6 Multipliers 302 10.7 Example of networks with standard arithmetic modules 304 10.8 Further readings 306        Exercises 306  TOP 11. STANDARD SEQUENTIAL MODULES 311 11.1 Registers 311 11.2 Shift registers 314 11.3 Counters 319 11.4 Multimodule systems 332 11.5 Further readings 333        Exercises 334 TOP 12. PROGRAMMABLE MODULES 339 12.1 Programmable sequential arrays (PSA) 340 12.2 Read-only memories (ROM) 343 12.3 Networks of programmable modules 347 12.4 Advantages and disadvantages of programmable modules 349 12.5 Field-programmable gate arrays (FPGAs) 350 12.6 Further readings 358        Exercises 358  TOP 13.  REGISTER-TRANSFER LEVEL (RTL) SYSTEMS 362 13.1 Execution graphs 362 13.2 Organization of systems 366 13.3 Specification of RTL systems using 370 13.4 Implementation of RTL systems 372 13.5 Analysis of RTL systems 376 13.6 Design of RTL systems 381 13.7 Further readings 392         Exercises 392  TOP 14. DATA AND CONTROL SUBSYSTEMS 398 14.1 Data subsystem 398        • Storage modules 399 • Register file • Random-access memory • Other storage modules         • Functional modules 402 • Datapaths 403 14.2 Control subsystem 405 14.3 A design example 409 14.4 Microprogrammed controller 412         • Structure of a microprogrammed controller          • Microinstruction format          • Example of microprogrammed system  14.5 Further readings 426        Exercises 426  TOP 15.  SPECIFICATION AND IMPLEMENTATION OF A MICROCOMPUTER 436 15.1 Basic components of a computer 437 15.2 Specification (architecture) of a simple microcomputer system 439 • Memory subsystem • Input/output (I/O) subsystem • Processor • Instruction sequencing • Condition setting • Specification of the memory contents  15.3 Implementation of a simple microcomputer system 457         • Memory subsystem         • Processor          • Register file          • Dedicated registers          • Arithmetic-logic unit         • Other modules          • Interconnections          • Events and flow of data 15.4 Operation of the computer and cycle time 464 15.5 Description of the processor implementation in VHDL 468         •  Data subsystem          •  Register file         •  Arithmetic-logic unit         •  Registers         •  Other modules in data subsystem          • Control subsystem  15.6 Further readings 478         Exercises 478 TOP Appendix A BOOLEAN ALGEBRAS 480 A.1 Boolean algebra 480 A.2 Switching algebra 481 A.3 Important theorems in Boolean algebra 482 A.4 Other examples of Boolean algebras 486 A.5 Further readings 487 TOP INDEX  489 Companion CD-ROM   Altera's MAX+PLUS II software (student edition), a complete CAD environment for the design of digital systems. MAX+PLUS II includes tools for design and simulation of digital systems, ranging from schematic capture to synthesis based on hardware description languages (Altera HDL and VHDL). The CD-ROM has documentation describing the features and use of the various tools. In addition, the CD-ROM contains the uVHDL source code of the examples used throughout the book. Several of those examples use VHDL packages from the standard IEEE library (ieee.std_logic_1164), which are included in the MAX+PLUS II support libraries. It should be noted that some of the uVHDL examples in the book correspond to high-level behavioral descriptions using constructs that might not be allowed in a synthesis environment; consequently, those examples might not be accepted by the MAX+PLUS II VHDL compiler. This is the case, in particular, for some of the descriptions in the later chapters of the book.TOP