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{\Large \bf 
An Excerpt From: \\
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`Partitioning Digital Circuits   \\
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for Implementation in Multiple FPGA ICs' \\
}
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{\normalsize \bf Roman Ku\v znar$^{1,2}$, Franc Brglez$^{1}$, Krzysztof
Kozminski$^{1}$} 
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\footnotesize{

\indent The following pages contain an excerpt from the MCNC Technical Report
named above. This information is provided in order to facilitate the use of
the Partitioning (Xilinx) benchmarks developed as part of the project
described in this MCNC Technical Report.

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Memoranda in this series are issued for early dissemination to MCNC,
its six Participating Institutions, and MCNC Industrial Affiliates.
They are not considered to be published merely by virtue of appearing
in this series.  This copy is for private circulation only and may not
be further copied or distributed.

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MCNC Technical Reports are routinely submitted for publication
elsewhere.  Their distribution outside the MCNC Community prior to
publication is limited to peer communications and specific requests.
References to this work should be made either to the published version,
if any, or in the form ``private communication.''

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For information about the ideas expressed herein, contact the author(s)
directly.  For information about the MCNC Technical Report Series, or
Industrial Affiliates Program, contact Corporate Communications, MCNC,
P.O. Box 12889, Research Triangle Park, NC 27709; 919-248-1842.

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\today

Technical Report TR93-03	
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\copyright 1993 MCNC
All Rights Reserved
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}

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\footnoterule
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{\footnotesize 
\noindent
        $^{1}$MCNC Center for Microelectronic Systems Technologies,
        P.O. Box 12889,
        Research Triangle Park, NC 27709 \\

\noindent $^{2}$ Department of Electrical and Computer Engineering,
University of Ljubljana,
                 Tr\v za\v ska 25, 61000 Ljubljana, Slovenia
}
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