All variables and structures that are used by the three
blocks (the {\em global} group) are first described.  Then the variables and structures
used by the D algorithm routines ({\em d\_alg} group), the fault collapsing 
routines ({\em fc} group) and the good circuit and fault simulators ({\em sim} group) are described.

For every group, all constants and data types, as found in
the "h" file are described, and then the description of the actual variables is
provided.

\subsection{System global variables}

\subsubsection{Constants}

boolean constants :
\begin{description}
\item[false] 0
\item[true] 1
\item[fail] 0
\item[success] 1
\end{description}

\noindent
string and pointer constants :
\begin{description}
\item[eos] 0
\item[null] 0
\end{description}

\noindent
circuit size parameters :
\begin{description}
\item[logic\_values] 5
\item[max\_gate\_number] 100
\item[max\_fan] 6
\item[max\_line\_number] max\_gate\_number*max\_fan / 2
\item[max\_clocks] 6
\item[max\_clock\_gates] max\_gate\_number / 4
\item[x\_ref\_length] 2*max\_line\_number - 1
\item[max\_timesteps] 1000
\end{description}

In order to limit list manipulation and dynamic storage allocation,  
arrays are used. Since these are allocated before the circuit is read, the circuit size 
parameters define the maximum allowed values for these parameters. In case some 
parameter exceeds its maximum allowed value, a message is generated and the 
maximum value must be changed and the whole system recompiled.

The circuit uses 5 logic values - {\em 0, 1, x, d, dbar}. The maximum number of
gates allowed is 100 and the maximum fan-in or fan-out per gate is 6. Since
every line is an output of one gate and an input of another, a bound on the
number of lines in the circuit is $max\_gate\_number*max\_fan / 2$. The maximum 
number of clocks in the circuit is 6, and a clock can drive no more than
$max\_gate\_number / 4$ elements. {\em x\_ref\_length} is the length of the 
{\em Hash} table
for line names and {\em max\_timesteps} is the maximum number of value changes 
per line per simulation.

\noindent
fault type constants :
\begin{description}
\item[sa\_0] 0
\item[sa\_1] 1
\item[fault\_free] 2
\end{description}

\noindent
logic value constants :
\begin{description}
\item[x] 3
\item[d] 4
\item[dbar] 5
\end{description}

The circuit uses 5 logic values. 0 and 1 represent logic values 0 and 1. 3, 4
and 5 represent the values {\em x, d} and {\em dbar}.

\noindent
gate type constants :
\begin{description}
\item[and] 0
\item[or] 1
\item[inv] 2
\item[nand] 3
\item[nor] 4
\item[xor] 5
\item[buf] 6
\item[dff] 7
\item[jkff] 8
\item[pi] 9
\item[po] 10
\end{description}

The system recognizes 11 gate types. {\em inv} is an inverter, {\em buf} is a 
single input multiple output buffer, and {\em pi} and {\em po} are primary 
input and primary output.

\noindent
delay value constants :
\begin{description}
\item[type\_rise] 0
\item[type\_fall] 0
\item[type\_hold] 0
\item[type\_setup] 0
\end{description}

All 11 gate types have a rise and fall delay (0-1 and 1-0 transition delay).
Clocked elements also have hold and setup requirements. All parameters have 
default values of 0.

\subsubsection{Data types}
The circuit is modeled as a directed graph. The gates, primary inputs and
primary outputs are the graph nodes. The lines are the graph edges.  
Therefore,  two data types are required to represent nodes and edges.

Nodes are represented as
\begin{verbatim}
typedef struct node
   { char user_name[8] ;
     int q ;
     int qnot ;
     int logic_count[logic_values] ;
     int rise_delay ;
     int fall_delay ;
     int setup_time ;
     int hold_time ;
     int marked ;
     int level ;
   } gate ;
\end{verbatim}

The fields of the structure are :
\begin{description}
\item[user\_name] A 7 character user name for the gate.
\item[q] all non-clocked gates have either a single input or a single output.
The number of that line is stored in this field. For a clocked element, the 
number of the line connected to the {\em q} output is stored in the field.
\item[qnot] Used only for clocked elements. Holds the number of the line 
connected to the {\em qnot} output.
\item[logic\_count] An array of size {\em logic\_values}. For each value it 
stores the number of inputs having that value. Used for calculating the output 
value of a non-clocked element.
\item[rise\_delay] The 0-1 transition delay of the element.
\item[fall\_delay] The 1-0 transition delay of the element.
\item[setup\_time] The required setup time for the element. Used only for 
clocked elements.
\item[hold\_time] The required hold time for the element. Used only for clocked 
elements.
\item[marked] A boolean field used during the D algorithm. If the field is 
{\em true}, any attempt to drive a fault through the gate is guaranteed to fail.
\item[level] The gate's level in the circuit. Equals the longest path to the 
gate from any primary input.
\end{description}

Before defining the edge type a subtype is needed

\begin{verbatim}
typedef struct t_val
   { int time ;
     int value ;
   } time_value ;
\end{verbatim}

This structures holds pairs of time and value, indicating that at time 
{\em time} the line was assigned the value {\em value}.

The edge type is

\begin{verbatim}
typedef struct edge
   { char user_name[8] ;
     int source ;
     int destination ;
     int value ;
     int fault ;
     time_value history[max_timesteps] ;
   } line ;
\end{verbatim}

The fields of the structure are :
\begin{description}
\item[user\_name] A 7 character user name for the line.
\item[source] A number representing the source gate of the line.
\item[destination] A number representing the destination gate of the line.
\item[value] The logic value of the line.
\item[fault] The fault value of the line.
\item[history] An array of all the changes in the line value.
\end{description}

\subsubsection{Data structures}
\noindent
\begin{verbatim}
gate gate_list[max_gate_number]
\end{verbatim}
\begin{quotation}
The internal name of all circuit gates is an integer. The integer value is
the index of the gate's structure in the {\em gate\_list[]} array.
\end{quotation}

\noindent
\begin{verbatim}
int fan_table[max_gate_number][max_fan+1]
\end{verbatim}
\begin{quotation}
A primary input {\em gate} has just one output line and no input lines. The 
internal
name of the output line is stored in the {\em q} field of the gate structure. A 
primary output gate has just one input line and no output line. The input line 
is stored in the {\em q} field of the structure.

A buffer has just one input line but multiple output lines, while all other
combinational gates have one output line but multiple input lines. The one
input (output) line of the gate is stored in the {\em q} field of the gate 
structure. The multiple input (output) lines are stored in {\em fan\_table[][]}.
If the gate name is $i$, then column $0$ of row $i$ holds the fan count while 
the following
columns hold the names of the fan lines, in the order in which they appear in
the circuit description file. 

For a clocked element there are at most two output lines, a {\em q} line and a
{\em qnot} line. The {\em q} and {\em qnot} fields of the element structure hold
the names
of theses lines. If a line is not connected to one of these outputs, the
corresponding field is -1. At least one output is connected to some line. 
For a D flip-flop, there can be up to four inputs, two of which are optional.
The four lines are the {\em clock, reset, preset} and {\em D} lines, with 
{\em reset} and {\em preset} being the optional lines. This is the order in
which they appear in the circuit description and the order in which they
appear in the element's row of {\em fan\_table[][]}, starting in column 0. If 
any of
the optional lines is missing, a -1 appears in its place. The same applies to
a JK flip-flop, except it can have five input line, two of which are optional. 
The lines are {\em clock, reset, preset, J} and {\em K}, with {\em reset} and 
{\em preset} being optional. 
\end{quotation}

\noindent
\begin{verbatim}
line line_list[max_line_number]
\end{verbatim}
\begin{quotation}
{\em line\_list[]} stores the line structures for all circuit lines. The 
internal line
name is its index in {\em line\_list[]}. The numbers are given in the order in 
which the lines are encountered in the circuit description.
\end{quotation}

\noindent
\begin{verbatim}
int line_x_reference[x_ref_length]
\end{verbatim}
\begin{quotation}
When a user name for a line is read, it must be converted to an internal name.
This is done with a {\em Hash} function and {\em line\_x\_reference[]} is the 
{\em Hash} table.
\end{quotation}

\noindent
\begin{verbatim}
int clk_table[max_clocks][max_clock_gates]
\end{verbatim}
\begin{quotation}
The circuit can have up to {\em max\_clocks} different clocks and each clock 
can drive up to {\em max\_clock\_gates} different gates. For each clock, 
{\em clock\_table[][]} stores the names of the elements driven by the clock.
\end{quotation}

\noindent
\begin{verbatim}
int clk_cntr[max_clocks]
\end{verbatim}
\begin{quotation}
For each clock, {\em clk\_cntr} stores the number of elements driven by that 
clock.
\end{quotation}

\noindent
\begin{verbatim}
char clk_names[max_clocks][8]
\end{verbatim}
\begin{quotation}
For each clock, {\em clk\_names[][]} stores its user name. The name can be at 
most seven characters long.
\end{quotation}

\noindent
\begin{verbatim}
int number_of_gates
\end{verbatim}
\begin{quotation}
Stores the number of gates in the circuit.
\end{quotation}

\noindent
\begin{verbatim}
int number_of_lines
\end{verbatim}
\begin{quotation}
Stores the number of lines in the circuit.
\end{quotation}

\noindent
\begin{verbatim}
int first_pi
\end{verbatim}
\begin{quotation}
In {\em gate\_list[]} there are three distinct blocks. The first is the block 
of all
combinational and clocked elements. It is followed by a block of all primary
inputs, which is followed by the block of all primary outputs. {\em first\_pi}
is the index, and name, of the first primary input gate.
\end{quotation}

\noindent
\begin{verbatim}
int first_po
\end{verbatim}
\begin{quotation}
{\em first\_po} is the index, and name, of the first primary output gate.
\end{quotation}

\subsection{D algorithm variables}

\subsubsection{Constants}

\noindent
action constants :
\begin {description}
\item[imply] 0
\item[drive] 0
\item[justify] 1
\end {description}

\subsubsection{Data types}

For the D algorithm three lists are maintained. The first is the list of
gates on the d-frontier. The second is the list of line justifications of the
j-frontier. The third list is a list of all implications, i.e. implied line
values and justifications added to the j-frontier, implied by a decision. This
list is maintained so that if backtracking occurs and the decision is cancelled,
the state of the circuit, before the decision, can be reconstructed.

A d-frontier structure is of type
\begin{verbatim}
typedef struct d_rec
   { struct d_rec *prev ;
     int gate ;
     struct d_rec *next ;
   } d_front_rec ;
\end{verbatim}

The fields of the structure are
\begin{description}
\item[prev] A pointer to the previous structure on the list.
\item[gate] The internal gate name of the d-front gate.
\item[next] A pointer to the next structure on the list.
\end{description}

To represent a line on the j-frontier we use

\begin{verbatim}
typedef struct j_rec
   { struct j_rec *prev ;
     int line ;
     struct j_rec *next ;
   } j_front_rec ;
\end{verbatim}

The fields of the structure are
\begin{description}
\item[prev] A pointer to the previous structure on the list.
\item[line] The internal line name of the j-front line.
\item[next] T pointer to the next structure on the list.
\end{description}

The line structure, in {\em line\_list[]}, holds the line value needing 
justification, so there is no reason to store it here also.

To represent an implication structure the following structure is used

\begin{verbatim}
typedef struct act_rec
   { struct act_rec *prev ;
     int site ;
     int action ;
     struct act_rec *next ;
   } imply_rec ;
\end{verbatim}

The fields of the structure are
\begin{description}
\item[prev] A pointer to the previous structure on the list.
\item[site] The internal name of line involved in the implied action.
\item[action] An integer having the value of either the constant {\em imply}
or the constant {\em justify}. The value determines whether the 
implication was a line assignment ({\em imply}) or the addition of a line to 
the j-frontier ({\em justify}).
\item[next] A pointer to the next structure on the list.
\end{description}

\subsubsection{Data structures}

\noindent
\begin{verbatim}
imply_rec *imply_ptr
\end{verbatim}
\begin{quotation}
For every decision made, there is a local variable pointing to the first
element of the implication list. Every level of recursive calls to the D
algorithm has its own implication list. The pointer {\em imply\_ptr} points to 
the last structure in the implication list of the current recursion level. 
\end{quotation}

\noindent
\begin{verbatim}
int d_front_count
\end{verbatim}
\begin{quotation}
{\em d\_front\_count} counts the number of gates on the d-frontier. This does 
not include primary outputs with values of {\em d} or {\em dbar}.
\end{quotation}

\noindent
\begin{verbatim}
int d_out_count
\end{verbatim}
\begin{quotation}
{\em d\_out\_count} counts the number of primary outputs with a value of 
{\em d} or {\em dbar}.
A non-zero value indicates that a fault has been propagated to a primary output.
If both this counter and {\em d\_front\_count} are zero then we must backtrack.
\end{quotation}

\noindent
\begin{verbatim}
int j_front_count
\end{verbatim}
\begin{quotation}
{\em j\_front\_count} counts the number of lines on the j-frontier.
When this counter is zero and {\em d\_out\_count} is greater than zero, a test 
vector has been found.
\end{quotation}

\noindent
\begin{verbatim}
d_front_rec *d_front_hdr, *d_front_last
\end{verbatim}
\begin{quotation}
These pointers point to the first and last elements of the d-frontier list.
\end{quotation}

\noindent
\begin{verbatim}
j_front_rec *j_front_hdr, *j_front_last
\end{verbatim}
\begin{quotation}
These pointers point to the first and last elements of the j-frontier list.
\end{quotation}

\noindent
\begin{verbatim}
int fault_gate
\end{verbatim}
\begin{quotation}
This variable hold the internal name of the destination gate of the faulty
line. It is used to ensure that when the fault is first-level excited (the
non-stuck-at value is first level justified, i.e. backward implication is
carried out as far back as possible) the gate output will not be set. If
the gate output is set, the fault cannot be later driven through this gate
and propagated to a primary output.
\end{quotation}

\noindent
\begin{verbatim}
int d_alg_error
\end{verbatim}
\begin{quotation}
A boolean flag indicating a fatal error occurred and the algorithm can not 
continue. An appropriate message will be generated. One such error is a 
flip-flop in the circuit, since the D algorithm works only on combinational
circuits.
\end{quotation}

\noindent
\begin{verbatim}
int step , trace
\end{verbatim}
\begin{quotation}
Boolean flags indicating whether one of the two special running modes, 
{\em step} or
{\em trace} is in effect. Both flags have default values of {\em false}.
\end{quotation}

\subsection{Fault collapsing variables}

\subsubsection{Data types}

During the fault collapsing process, several lists will be created and
maintained. All lists will have the same element type :
\begin{verbatim}
typedef struct f_rec
   { struct f_rec *prev ;
     int fault ;
     int line ;
     struct f_rec *next ;
   } fault_rec ;
\end{verbatim}

The fields of the structure are
\begin{description}
\item[prev] A pointer to the previous element on the list.
\item[fault] A 0 or a 1 indicating whether the fault is a {\em sa-0} or 
{\em sa-1}.
\item[line] The internal name of the faulty line.
\item[next] A pointer to the next element on the list.
\end{description}

\subsubsection{Data structures}

\noindent
\begin{verbatim}
fault_rec *redundant_list
\end{verbatim}
\begin{quotation}
This pointer points to the next available element in the {\em redundant} fault
list (the last element, which has all its fields set to {\em null}).
This is a list of faults for which our test generation algorithm failed to
produce a test.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *redundant_hdr
\end{verbatim}
\begin{quotation}
A pointer to the first element of the redundant list.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *fault_list
\end{verbatim}
\begin{quotation}
This pointer points to the next available element in the {\em fault} 
list (the last element, which has all its fields set to {\em null}).
This is a list of faults for which we try to generate tests.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *fault_hdr
\end{verbatim}
\begin{quotation}
A pointer to the first element of the fault list.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *dominant_list
\end{verbatim}
\begin{quotation}
This pointer points to the next available element in the {\em dominant} fault
list (the last element, which has all its fields set to {\em null}).
This is a list of faults which represent dominating equivalence classes.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *dominant_hdr
\end{verbatim}
\begin{quotation}
A pointer to the first element of the dominant list.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *equivalence_reps
\end{verbatim}
\begin{quotation}
This pointer points to the next available element in the 
{\em equivalence representatives}
list (the last element, which has all its fields set to {\em null}).
Each fault on this list belongs to a different equivalence class and we
start constructing the class with this element.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *reps_hdr
\end{verbatim}
\begin{quotation}
A pointer to the first element of the equivalence representative list.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *equivalence_list
\end{verbatim}
\begin{quotation}
This pointer points to the next available element in the 
{\em equivalence representatives}
list (the last element, which has all its fields set to {\em null}).
All faults on this list belong to the same equivalence class and are waiting
their turn to be processed, i.e. are their corresponding input faults in the
equivalence class or do they belong to new equivalence classes.
\end{quotation}

\noindent
\begin{verbatim}
fault_rec *equivalence_hdr
\end{verbatim}
\begin{quotation}
A pointer to the first element of the equivalence list.
\end{quotation}

\noindent
\begin{verbatim}
int equivalence_table[8][max_line_number]
\end{verbatim}
\begin{quotation}
All equivalence-dominance relations between all stuck-at faults are stored
in the equivalence table. Each column represents a line. Each integer entry
represents a fault. An entry of $2i$ represents that line $i$ is stuck at 0.
An entry of $2i+1$ represents line $i$ stuck at 1.

All faults in an equivalent class are arranged in a pointer loop, i.e. each
fault points to another fault in the class and by going around the loop, the
whole class is encountered.

Row 0 (1) contains a stuck at 0 (1) equivalence pointer. 

Row 2 (3) contains the representative of the stuck at 0 (1) equivalence class.

Row 4 (5) contains a fault dominating the stuck at 0 (1) fault. If no such
dominating fault exists, the entry is -1.

If line $i$ stuck at 0 (1) is an equivalence class representative, then row 6 
(7) contains the number of faults dominated by the stuck at 0 (1) fault. If
it is not a representative, the entry is -1. When a test for a dominated fault
is found, the count of the dominating representative, through the whole 
dominating chain, is changed to -1. When a test for a dominated fault can not
be generated, the count of the dominating representative is decreased by 1. If
the count reaches 0, the fault is added to the list of fault for whom we must
find a test vector (since no test was found for all the dominated faults).
\end{quotation}

\noindent
\begin{verbatim}
int active
\end{verbatim}
\begin{quotation}
Represents the current fault begin processed in the fault collapsing process.
\end{quotation}

\noindent
\begin{verbatim}
int first
\end{verbatim}
\begin{quotation}
The first fault of an equivalence class. Also the class representative.
\end{quotation}

\noindent
\begin{verbatim}
int dominant
\end{verbatim}
\begin{quotation}
A boolean flag indicating whether the equivalence class dominates any other 
class. Initiated to false when the processing of the class begins. If the 
class does not dominate another, the class representative is added to the
representative list. If the class does dominate some other class, the 
representative is placed on the dominant list.
\end{quotation}


\subsection{Good Circuit Simulator variables}

\subsubsection{Constants}

\noindent
action constants :
\begin {description}
\item[init] 0
\item[add] 1
\item[pick] 2
\end {description}

\subsubsection{Data types}

During event-driven simulation, three lists are maintained. The first is an 
event-list which stores the list of events to be processed at each timestep.
The other two are sets - the {\bf activated set} which is a set of gates
activated by the current event and the {\bf scheduled events set} which is
a set of events scheduled by the current event.

An event structure is of type
\begin{verbatim}
typedef struct event_node
{ int line;
  int value;
  struct event_node *next;
} event;
\end{verbatim}

The fields of the structure are
\begin{description}
\item[line] The internal line name on which the event occurs
\item[value] The value which the line takes as a result of the event
\item[next] A pointer to the next structure on the event-list
\end{description}

Each element of the Activated Set is of type
\begin{verbatim}
typedef struct gate_element
{ int gate;
  struct gate_element *next;
} activated_gate;
\end{verbatim}

The fields of the structure are
\begin{description}
\item[gate] The internal gate name of the gate activated by the event
\item[next] A pointer to the next structure in the list
\end{description}

Each element of the Scheduled Events' set is of type
\begin{verbatim}
typedef struct event_element
{ int line;
  int value;
  int time;
  struct event_element *next;
} scheduled_event;
\end{verbatim}

The fields of the structure are
\begin{description}
\item[line] The internal line name of the line on which the event is scheduled
\item[value] The value the line is to take
\item[time] The time at which the event is scheduled to take place
\item[next] A pointer to the next structure in the list
\end{description}


\subsubsection{Data structures}
\noindent
\begin{verbatim}
int time
\end{verbatim}
\begin{quotation}
{\em time} counts the simulation time. It is incremented every timestep.
\end{quotation}

\noindent
\begin{verbatim}
int simulation_length
\end{verbatim}
\begin{quotation}
This variable holds the total simulation time.
\end{quotation}

\noindent
\begin{verbatim}
int number_of_events, number_gates_act
\end{verbatim}
\begin{quotation}
These variables hold the total number of events simulated and the number of gates 
activated during the simulation run, respectively. The variables are for
statistical data of the simulation run.
\end{quotation}

\noindent
\begin{verbatim}
event *next_event, *present_event
\end{verbatim}
\begin{quotation}
{\em present\_event} is a pointer to the current event and {\em next\_event} is
a pointer to the next event to be processed.
\end{quotation}

\noindent
\begin{verbatim}
event *event_list[max_timesteps]
\end{verbatim}
\begin{quotation}
Each element of the array {\em event\_list} is a linked list of events
corresponding to that timestep. During simulation, for every timestep, time is
advanced and events are picked up from the event list to be processed. Also
newly scheduled events are places in the list corresponding to the scheduled time.
\end{quotation}

\noindent
\begin{verbatim}
activated_gate *activated_set
\end{verbatim}
\begin{quotation}
This is a pointer to the first element of the activated set of gates.
\end{quotation}

\noindent
\begin{verbatim}
scheduled_event *scheduled_event_set
\end{verbatim}
\begin{quotation}
This is a pointer to the first element of the  set of new events to be
scheduled.
\end{quotation}


\noindent
\begin{verbatim}
char step_flag, act_flag, event_flag, list_flag, line_flag
\end{verbatim}
\begin{quotation}
These are flags indicating user responses to questions asked for display of 
information during simulation in the {\bf step} mode. {\em act\_flag} 
represents the activated set, {\em event\_flag} represents current event,
{\em list\_flag} represents the event list and {\em line\_flag} represents
line values to be displayed. Depending upon the user responses these flags are 
set and information displayed.
\end{quotation}

\noindent
\begin{verbatim}
int observe_lines[max_line_number/5]
\end{verbatim}
\begin{quotation}
This array holds the internal line names of the lines which the user wants to
observe during the simulation run. The value of the lines in this array is printed
out after every event is processed.
\end{quotation}


\subsection{Fault simulator variables}

\subsubsection{Constants}

\noindent
\begin{description}
\item [INTSIZE] 32
\item [MAXINTS] 256
\item [ALLONES] 1
\item [NINTS] (max\_line\_number + INTSIZE)/INTSIZE
\end{description}

\subsubsection{Data types}

The deductive fault simulation algorithm drops faults after simualtion of a 
test vector. An array of structures {\em d\_fault} is used to keep a track
of the faults to be dropped.

\begin{verbatim}
typedef struct fault
{  int line;
   int value;
}d_fault;
\end{verbatim}

The fields of the structure are
\begin{description}
\item [line] Internal line name of the line 
\item [value] The stuck\_at value of the line which is detected as a fault by the
current test vector.
\end{description}


\subsubsection{Data structures}

\noindent
\begin{verbatim}
int sim_f_list0[MAXINTS], sim_f_list1[MAXINTS]
\end{verbatim}
\begin{quotation}
{\em sim\_f\_list0} is an array represnting the {\em sa\_0} faults to be
simulated. It is an array of integers and each {\em bit} of an integer corresponds
to a line. If the bit is set, that line {\em sa\_0} is to be simulated. 
Similarly, {\em sim\_f\_list1} is for {\em sa\_1} faults.
\end{quotation}


\noindent
\begin{verbatim}
int number_detected_faults, number_test_vectors
\end{verbatim}
\begin{quotation}
These variables are used for counting the number of faults detected and the total
number of test vectors simulated. Statistical information like fault coverage
can be calculated from these variables.
\end{quotation}

\noindent
\begin{verbatim}
int cntrl_value
\end{verbatim}
\begin{quotation}
While finding the output fault list of every gate, this variable is set to 1, if
an input line has a controlling value, else it is set to 0. Input fault list
manipulation is then done depending upon this value.
\end{quotation}

\noindent
\begin{verbatim}
FILE *vector_file
\end{verbatim}
\begin{quotation}
A pointer to the file containing the test vectors.
\end{quotation}

\noindent
\begin{verbatim}
d_fault faults_to_drop[max_line_number]
\end{verbatim}
\begin{quotation}
An array of structures representing the faults to be dropped after simulating a 
test vector.
\end{quotation}

\noindent
\begin{verbatim}
int ckt_depth
\end{verbatim}
\begin{quotation}
This variable stores the depth of the circuit after the circuit is levelized.
\end{quotation}









