I am a PhD candidate at UCLA. My research is focused on the design of scalable and adaptive distributed systems targeting edge networks and the Internet-of-Things. Other interests include mobile computing, health analytics, probabilistic reasoning, effective sampling, and computer systems design and architecture.
Under the IoBT (Internet-of-Battlefield-Things) and CONIX (Computing on Network Infrastructure) centers, my research has shifted towards designing and building adaptive distributed systems. The overarching vision is to impart self-awareness into cloud-edge systems, such that they may be resilient to any deployment environment. I began with DDFlow, a macroprogramming abstraction that enables high-level succinct application expression and flexibility in system execution. Next, I created a key-value datastore system that incorporates the notion of adaptive data placement, such that the system learns where to optimally serve data based on how it is accessed. Finally, in collaboration with Lab11 at UC Berkeley, we are building a novel resource manager for systems spanning edge networks. Our agent process can be deployed on Cortex-M microprocessors, lifting sensor networks up into the general-purpose resource cluster.
As part of the Mobile Sensor Data-to-Knowledge project, developed an optimized sensor storage platform that provides near-optimal write throughput. Introduced Nanoflow, a full IoT/mobile system for providing efficient sensor analytics at the edge. Due to the unique nature of sensor data processing in the highly limiting mobile environment, Nanoflow's key abstraction is the dataflow programming paradigm, which enables effective code re-use and an intuitive programming environment.
Researched cache optimizations. Updated internal cache simulator to model current GPU architecture. Explored transaction reordering and compression algorithms for the next generation architecture. (C++)
Explored interconnect networks and datacenter applications. Studied and improved upong previous work on a hybrid wired/wireless on-chip interconnect network. Considered new topologies, flow control and adaptive routing. Modeled ideas on a modified Garnet network simulator (C++)
Worked in device integration and automation. Created a program to integrate hardware devices used for electron microscopy. Automated search/scan algorithms using feedback loops. Tuned program based on hardware limitations to maximize scan speed. Integrated with visualization tools. (C++, Matlab)
Worked in simulator development. Ported an old SPARC architecture simulator with a specialized accelerator setup to a new x86-64 simulator. Created custom instruction for an LCA device that can use DMA, send CPU interrupts, and perform specialized functions. (C++, Python)
GPA: 4.0
GPA: 4.0
GPA: 3.80
