Vdiff - A Program Differencing Algorithm for Verilog HDL

Verilog Diff (Vdiff) is a position-independent differencing alogrithm for Veirolog HDL language instantiated as an Eclipse plug-in.

During code review tasks, comparing two versions of a hardware design description using existing program differencing tools such as diff is inherently limited because existing program differencing tools implicitly assume sequential execution semantics, while hardware description languages are designed to model concurrent computation. We designed a position-independent differencing algorithm to robustly handle language constructs whose relative orderings do not matter. This paper presents Vdiff, an instantiation of this position-independent differencing algorithm for Verilog HDL. To help programmers reason about the differences at a high-level, Vdiff outputs syntactic differences in terms of Verilog-specific change types. We evaluated Vdiff on two open source hardware design projects. The evaluation result shows that Vdiff is very accurate, with overall 96.8% precision and 97.3% recall when using manually classified differences as a basis of comparison. Vdiff makes the following contributions:

• Vdiff uses a position-independent differencing algorithm to robustly handle language constructs whose relative orderings do not matter such as statements with concurrent execution semantics.
• Vdiff produces accurate differencing results with 96.8% precision and 97.3% recall when using manually classified differences as a basis of evaluation.
• Vdiff outputs syntactic differencing results in terms of Verilog-specific change types to help programmers better understand the differences.

Click here to download Vdiff.
Click here to view paper.

Screenshots

NOTE: click on screenshots for higher resolution pictures

Screenshot #1: VerilogDiff showing menu for comparison between revisions of uart_receiver.v

Screenshot #2: VerilogDiff showing wire removal in uart_receiver.v

Screenshot #3: VerilogDiff showing additional condition added to if statement in uart_receiver.v

Screenshot #4: VerilogDiff showing additional condition added to if statement in uart_receiver.v, after double clicking on structural difference in tree

Download

Vdiff is an Eclipse plug-in. Download the source here: vdiff_v0.1.0.zip

To download Vdiff as a binary with Eclipse's "Help->Install New Software" method, use this update site: http://users.ece.utexas.edu/~miryung/software/vdiff/update (Coming Soon!)

Install Guide

1. Download and install a version of Eclipse that includes the Plugin Development Environment (PDE). We used: Eclipse 2.6 for RCP
2. Download and install: Java 6 SDK
3. Download and install: JavaCC 5.0
4. Extract Vdiff_v0.1.0.zip to the directory you installed Eclipse into (for example: C:\Program Files\eclipse-3.6.0). This will put net.sourceforge.veditor_0.1.0.jar into the plugins\ subdirectory
   
   
   
5. Start/Restart Eclipse (yes, you must restart)
6. Create a new project by selecting "New->Other..."
   
   
   
7. Select "Verilog/VHDL->Verilog/VHDL project" as your new project
   
   
   
8. Create a project named "Uart_16550"
   
   
   
9. Select "File->Import..." and select "General->File System"
   
   
   
10. Browse to where you have your input files:
    
    
    
11. "Select All" and click finish:
    
    
    
12. Select 2 files and right-click. Then select "Compare With->Each Other"
    
    
    
13. See structural diff in top window, syntatic diff in middle window, and categorization of change types in bottom window
    
    
    

Links

• Veditor - Eclipse Verilog editor, project which Vdiff is derived from
• Eclipse - Homepage
• Java 6 SDK
• JavaCC 5.0