CS 258F Winter 1995
	Class Project -- Partitioning Circuits Into Multiple FPGAs
		    Instructor:  Prof. Jason Cong


Requirements of the project:
---------------------------
* You need to partition the ten circuits under 
	/u/class/layout/multiway_partition/project95w/Circuits
  into multiple FPGAs in Xilinx 3000 family so that the total cost of the
  FPGAs is minimized.
 
* You need to find a partner to form a two-person team to work on the project.
  Since there are twelve students in the class, we'll have six teams in total.
  The final results from all six teams will be compared, and the quality
  of your result determines partially your grade of the project.
 
* You need to turn in a class project report by 5pm of March 24 (Fri.).
  A typical report has about 10 pages, including a brief summary of related
  work on this topic, detailed description of your approach, justification of
  your approach,  your results, and a breakdown of each teammate's contribution
  to the project.  Please use figures and tables effectively to improve the 
  quality of your presentation.  Each team needs to turn in only one report.


Description of test circuits:
----------------------------
* The ten test circuits are all combinational circuits.  They are going to be
  partitioned into multiple FPGAs in Xilinx 3000 family.

* Each gate in test circuits has no more than five inputs, and it will
  occupy a 5-input lookup-table (5-LUT) on Xilinx 3000 family FPGAs.

* The ten circuits under 
        /u/class/layout/multiway_partition/project95w/Circuits
  are grouped into two directories: minarea/ and mindepth/.  The circuits
  under the two directories have the same names. In fact, they are logically
  equivalent circuits, optimized for area minimization and depth minimization,
  respectively, during the technology mapping step.  

* The sizes of ten test circuits are as follows

  circuit         #PI     #PO         #levels                 #5LUTs
                                  minarea mindepth        minarea mindepth
  ------------------------------------------------------------------------
  c880             60      26        12       7              103     133
  c2670           233     140        11       7              295     305
  c3540            50      22        18      10              317     482
  c5315           178     123        10       8              460     519
  c7552           207     108        10       6              637     727
  

  (The FlowMap algorithm was used for technology mapping to generate the
  depth-optimized test circuits.  The DF-map algorithm was used for technology 
  mapping to generate the area-optimized test circuits.  A number of 
  post-processing operations were applied to further the number of 5-LUTs
  after FlowMap and DF-Map.  Both the FlowMap and DF-Map algorithms were 
  developed at UCLA by Cong and Ding.)

* The format of each test circuit is specified in the file
	/u/class/layout/multiway_partition/project95w/netlist.format


Description of Xilinx 3000 FPGAs
--------------------------------
You may use the following FPGAs from the Xilinx 3000 family:

  Device		Type No.	# 5-LUTs	# IOs	Cost(relative)
  ----------------------------------------------------------------------------
  XC3020		1		64		64	1
  XC3030		2		100		80	1.36
  XC3042		3		144		96	1.84
  XC3064		4		224		110	3.15
  XC3090		5		320		144	4.83



Your Results
------------

*  For each circuit, you need to show the number of FPGAs you used for each
   type and the total cost.  The first objective is to minimize the total cost.

*  For each circuit, you need to show the utilization of FPGA in terms of
   number of 5-LUTs used and number of IO blocks used.  You also need to show
   the total number of nets being cut.  The second objective is to minimize
   the number of nets being cut.

-------------------------------------------------------------------------------
Jason Cong	2/27/95