I am a Systems Research Engineer in the SRG group at Google.
Prior to that, I did my Ph.D. at the University of California Los Angeles, advised by Prof. Tony Nowatzki. My research is about rethinking the accelerator design to achieve general-purpose acceleration using reconfigurable architecture.
I worked on designing programmable irregular accelerators by finding fundamental data-dependence forms in an architecture called Sparse Processing Unit (SPU). I enhanced the flexibility of SPU using the "TaskFlow" execution model that supports fine-grained dynamic parallelism very efficiently, making it suitable for a variety of graph processing workloads. The architecture is called PolyGraph. My works on SPU and PolyGraph received IEEE Micro Top Picks Awards which is given to 12 papers in the field each year, based on novelty and long-term impact. The awards were given for developing a systematic understanding of the hardware-software co-design space. The recent work, "TaskStream: Accelerating Task Parallel Workloads by Recovering Program Structure" develops a task-parallel programming model integrated with the conventional dataflow model such that we can program SPU and PolyGraph workloads in TaskStream while exploiting the performance advantage of dynamic work distribution for medium granularity tasks.
During my internships, I gained experience in performance characterization of various industrial architectures -- Configurable Spatial Accelerator (CSA) at Intel, Edge Tensor Processing Unit (TPU) accelerator for ML at Google, and Microsoft's Azure Synapse Spark for analytical database processing.
Before joining UCLA, I did my undergraduate studies at the Indian Institute of Technology Roorkee in Electronics and Communication Engineering with minors in Computer Science (2017). During my undergraduate, I worked with Prof. Onur Mutlu on designing memory scheduling techniques to mitigate inter-application interference.
You can find my Curriculum Vitae here.