Compute Express Link (CXL) has emerged as a pivotal interconnect for memory expansion. Despite its potential, the performance implications of CXL across devices, latency regimes, processors, and workloads remain underexplored. We present Melody, a framework for systematic characterization and analysis of CXL memory performance. Melody builds on an extensive evaluation spanning 265 workloads, 4 real CXL devices, 7 latency levels, and 5 CPU platforms. Melody yields many insights: workload sensitivity to sub-µs CXL latencies (140–410ns), the first disclosure of CXL tail latencies, CPU tolerance to CXL latencies, a novel approach (Spa) for pinpointing CXL bottlenecks, and CPU prefetcher inefficiencies under CXL.

Prior in-storage computing (ISC) solutions show fundamental drawbacks when applied to GNN acceleration: they obey a strict ordering of GNN neighbor sampling, failing to utilize flash internal parallelism; the I/O sizes generated by GNN are much smaller than the minimum flash access granularity, wasting channel bandwidth; and they rely on firmware-based request processing, constraining backend I/O throughput by the embedded core. We propose BeaconGNN, an ISC design for GNN that supports both large-scale graph structures and feature tables. It uses a novel graph format to enable out-of-order GNN neighbor sampling, and deploys near-data processing engines across the flash hierarchy (controller, channel, die). A spatial accelerator attached to the device bus accelerates GNN computation. BeaconGNN achieves up to 11.6× higher throughput and 4× better energy efficiency than the state-of-the-art ISC design.

Spatial accelerators provide massive parallelism with an array of homogeneous PEs, and enable efficient data reuse with PE array dataflow and on-chip memory. Existing accelerator generators fail to exploit the entire memory-level reuse opportunities and generate suboptimal designs with data duplication and inefficient interconnection. We propose EMS, an efficient memory subsystem synthesis and optimization framework for spatial accelerators. We use space-time transformation (STT) to analyze both PE-level and memory-level data reuse, and develop an algorithm to automatically generate the multi-banked scratchpad data layout, data mapping, and access controller. The generated memory subsystem supports direct, multicast, and rotated PE–memory interconnection topologies. EMS synthesizes tensor algebra to hardware in Chisel, reducing on-chip memory size by 28% on average over the state-of-the-art with comparable performance.

Accelerating tensor applications on spatial architectures provides high performance and energy-efficiency, but requires accurate performance models for evaluating various dataflow alternatives. Recent compute-centric and data-centric notations describe dataflow using imperative directives, but are less expressive and lead to limited optimization opportunities and inaccurate performance models. We propose TENET, a framework that models hardware dataflow of tensor applications using a relation-centric notation that formally describes hardware dataflow, PE interconnection, and data assignment in a uniform manner. The relation-centric notation is more expressive via sophisticated affine transformations and inherently supports accurate metric estimation (data reuse, bandwidth, latency, energy) by counting relations with integer set structures. TENET achieves 37.4% and 51.4% latency reduction for CONV and GEMM kernels over the state-of-the-art data-centric notation.