Computer Science Department
CS 151C - Design of Digital Systems
VHDL Projects on XSV Board
Professor: Dr. Leon Alkalai
TA: Ninoslav Stojcic
This is a set of projects developed by undergraduate students of Computer Science Department at University of California, Los Angeles.
Projects were implemented on XSV boards v1.1 by XESS Corp, with XCV50 Virtex FPGA (50K) Xilinx Inc. VHDL code was developed and tested within ISE Foundation 5.2.
For the first time, students of CS 151C (Design of Digital Systems) implemented their ideas in real hardware, since previous course incarnations have relied only on software verification. We do not guarantee that all of the projects are complete or entirely functional. Limitations occurred due to malfunctions in XSV boards or lack of available number of programmable gates in the FPGA. Still, we hope that these projects will serve as a pool of interesting ideas and a reference to difficulties that arise in implementations in ISE Foundation 5.2 and/or XSV Boards.
Majority of the designs incorporated some portion of VHDL code from VHDL XSV Board Interface Projects of students working for the School of Computer Science and Electrical Engineering in the University of Queensland, Australia. We found this resource extremely useful and we would like to express our appreciation that these often used XSV board interfaces were made publicly available.
Project files are in zip format, containing Power Point presentation, class report and VHDL code.
List of projects:
Descriptions and links to files
Adaptive Differential Pulse Code Modulation Decoder/Encoder Hardware Implementation
Adam Kaplan and Serge Baltayan
The DVI Adaptive Differential Pulse Code Modulation (ADPCM) algorithm was first described in an IMA recommendation on audio formats and conversion practices . ADPCM is a transformation that encodes 16-bit audio as 4 bits (a 4:1 compression ratio). In order to achieve this level of compression, the algorithm maintains an adaptive value predictor, which uses the distance between previous samples to store the most likely value of the next sample. The difference between samples is quantized down to a new sample using an adaptive step-size. The algorithm in  suggests using a table to adapt this step-size to the analyzed data. ADPCM has become widely used and adapted, and a variant of the algorithm performs voice encoding on cellular phones (allowing minimal data to be sent across the wireless network and increasing throughput).
 IMA Digital Audio Focus and Technical Working Groups, “Recommended Practices for Enhancing Digital Audio Compatibility in Multimedia System: Revision 3.00,” IMA Compatibility Proceedings, Vol. 2, Number 2, October 1992. back
Way Chung Cheng, Chan Chi Hong Patricio, Katherine Oey and Eduardo Tang
This game is a simplified version of the game “BeatMania” find in the arcade. The game starts with four columns on the screen. Bars will fall from the top of the screen to the bottom in those columns, according to the pattern entered in the pattern generator. There are four buttons on the XESS board, each button represents one column on the screen. Player has to press the corresponding buttons as the bars reach the base bar at bottom of the screen. If the button is pressed correctly, the column containing that bar will flash green, and the player will score one point.
When the game ends, a grade will be displayed on the screen. There are three grades, A, B, and F. If the player pressed twenty or more bars correctly, grade A is given. If the player pressed ten to nineteen bars correctly, grade B is given. Otherwise, grade F is given. That's basically it. Simple and fun. back
VHDL Checkers Implementation
Ibrahim Elbouchikhi and Amir Nader-Tehrani
Checkers is a game of two players, each have a certain number of initial players. The goal of the game is to be the last player standing, meaning that whoever eliminates all of the pins of the other player wins. This implementation is no different and is very close to the real game where the player can move in four different diagonal directions and can either move by one unit in each direction or jump over the opponent thus eliminating of his players. back
Enhanced Audio Project
Dixie Xue and Wei Zhang
This audio project contains a total of six files, which includes remap.vhd, audiotop.vhd, audio.vhd, player.vhd, recorder.vhd, and scraminterface.vhd file. It has about 99% of total slice registers. Due to limitations in the clock speed multiplier selections, the audio project samples at a frequency of 48.8 kHz instead of the normal 48kHz that would be used. This project allows recording and playback of just over 10 seconds of sound. Additionally, we have enhanced it with some amplitude effects, such as volume control and panning, and some time delay effects, such as echo and phasing. Those effects VHDL codes were been modified in remap.vhd, audiotop.vhd and audio.vhd. We set the default precision as 16 bits. The volume control has 4 scales, each one double or halved the current input data. The panning can be happened to shift left or shift right, which is also contained in any scale of volume. The echo effect can be run in any scales as well. It was tried to implement with noise gating to reduce the noise. The noise reduction would be operated when it detects the input data is out of the range of silent bits. back
CRC-8 Error Check
Daniel D. Chia and Adrian A. Javelo
CRC-8 is an algorithm in which a polynomial (Cx = X8 + X2 + X + 1) is used to calculate a CRC value that can be used to detect errors in an incoming bit stream. The goal of our project is to use the CRC-8 algorithm to enable a sender to calculate and append a CRC byte to the end of a data packet. When the receiver gets the data, it too calculates its own CRC byte and then compares it to the incoming CRC byte. If the two CRC bytes do not match, an error flag is raised. back
Electric Guitar Digital Effects Processor
This project is a VHDL implementation of an effects processor commonly used by electric guitarists and bassists in many genres of music. It incorporated several components of a Xess XSV-300 Board, including the Xilinx XCV50 Virtex FPGA, a single 512x16 SRAM bank, and a stereo input/output with an AK4520A codec. Functions include digital delay (echo), reverberation, flange and a distortion. The module is fully functional, as a guitar can be connected to the input, and an amplifier/speaker combination can be connected to the output. Implemented Audio Effects: Distortion, Reverb, Delay and Flanger. back
The Game of Life
Eric Hendrickson and Michael Parker
Researchers have recently been focusing on the property of “emergence” in collective systems – the way in which local interactions using simple rules build on one another to produce global change. Such properties can be found in our everyday life, making emergence an interesting topic to study: An ant, for example, only has contract with other ants immediately close to it, and yet through millions of these disparate local interactions a large, organized phenomena emerge. A well-researched model of such interaction is the Game of Life, by the mathematician Dr. John Conway. We chose to implement this game as our project its underlying rules are simple enough to implement in VHDL, while still generating complex global patterns through local interactions.
The Game of Life is not like most games, in that there are no winners or losers. Instead, an empty grid is presented to the user. In theory, the Game of Life should be played on a grid of infinite size – we must compromise due to space constraints, and adopt a 64 x 128 grid. Each cell in the grid can have two states, either “alive” or “dead.” Internally, the distinction between alive and dead is a 1 and a 0; to the user, a cell is filled (black) if alive, and empty (white) if dead. The user sets what cells should be initially alive, and what cells should be dead. Once a pattern has been decided upon, the game is run. When this happens, rules transform the grid from one state to the next. The new state of any cell depends upon its old state, as well as the states of its eight surrounding cells (including the diagonals). back
GIF Image Viewer
Erik Leung and Michael Mantel
A system is described that processes a GIF file stored in memory and displays the resulting image on a monitor connected to the VGA port. This demands an understanding of the VGA display system, the structure of a GIF file, and the LZW decompression algorithm, which is required to extract the compressed pixel data from the file. back
Computer Graphics:Where Straight Lines, Aren’t
Lorraine Jong, Lisa Shirachi and Sherman Wang
Our first algorithm is the Digital Differential Analyzer which requires floating-point intermediate values. Our second is the Midpoint Line Algorithm, a special case of Bresenham's Line Algorithm, which is famous for its speed and accuracy. back
Maze Generator and Maze Solver
Cindy Chiang, Lan Christine Do and Jacquelyn Leong
Based on the well known depth first search algorithm, our project automatically generates a perfect maze and then finds the path to solve it. A perfect maze is defined to have one and only one path from any point in the maze to any other point in the maze. It does not have any inaccessible sections, circular paths, or open areas. back
Video Equalizer of Audio Input
Wen Hsu and Aneesh Singhal
We basically took the idea from the
WinAmp mp3 player. When a user plays mp3s or any other supported audio file,
one can open the equalizer and choose from different visualization options that
allow them to select whatever video output they prefer. back
XESS Corporation - Board manufacturer
Xilinx - FPGA manufacturer
University of California Los Angeles
Computer Science Department at UCLA ...back